A flat panel display has developed rapidly because of its ultrathin and energy saving. Most of the flat panel displays use shift registers. Currently, the shift register realized by a GOA (Gate on Array) method not only can be integrated on a gate driving Integrated Circuit (IC) but also can cut down a manufacture procedure for a display panel, therefore it saves cost. As a result, the GOA technique has been applied widely to a manufacture process for the flat panel display recently.
FIG. 1 illustrates an existing design scheme of GOA comprising a plurality of shift registers S/R(1), S/R(2), S/R(3), . . . , S/R(N) layered and connected in cascade. Each shift register S/R(n) (1≦n≦N) outputs a scanning signal to a corresponding gate line G(n) through its own signal outputting terminal OUTPUT, and outputs the scanning signal to a resetting signal terminal RESTE of the S/R(n−1) and a signal inputting terminal INPUT of the S/R(n+1), the scanning signal performs a resetting function and a start function for the S/R(n−1) and the S/R(n+1), respectively, wherein the S/R(1) is inputted a frame start signal STV through its own signal inputting terminal, and the respective shift registers are input a reference voltage through the reference signal terminal VSS, so that an object of progressive scanning can be realized.
A schematic diagram of an inner structure of the above shift register unit S/R(n) is shown in FIG. 2. As shown in FIG. 2, the shift register consists of 12 Thin Film field effect Transistors (TFT) (labeled as M1, M2, M3, M4, M5, M6, M8, M9, M10, M11, M12 and M13 in FIG. 2, respectively) and one capacitor CAP (labeled as C1 in FIG. 2), and its corresponding control timing diagram is as illustrated in FIG. 3. For each shift register unit S/R(n), it may be in three control states as follows: (1) the inputting terminal INPUT and a clock signal CLKB are at a high level, a clock signal CLK is at a low level, and the M1, M13, M9, M8, M5, M6 and M12 are in a turned-on state and other TFTs are in a turned-off state at this time thereby the inputting terminal INPUT inputs a signal in this case and thus the outputting terminal OUTPUT outputs a low level signal since the CLK is at the low level; (2) the inputting terminal INPUT and the CLKB are at the low level, the CLK is at the high level, and the M3, M9, M5, M6 and M8 are in the turned-on state and other TFTs are in the turned-off state at this time thereby the outputting terminal OUTPUT outputs a high level signal in this case; (3) the CLKB is at the high level, the inputting terminal INPUT and the CLK are at the low level, and the M13, M12, M11, M10, M2, M4, M5 and M9 are in the turned-on state and other TFTs are in the turned-off stage at this time thereby a resetting operation is performed for a shift register unit at a previous stage in this case.
It can be seen from the description above that since the shift register unit at the Nth stage uses an output signal of the shift register unit at the (N−1)th stage as an input signal, the outputting terminal OUTPUT of the shift register unit at the Nth stage will output noise due to the existence of the capacitor C1 when the shift register unit at the Nth stage is in the first control state described above.